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general description the max8709/max8709a integrated backlight controller are optimized to drive cold-cathode fluorescent lamps (ccfls) using a resonant full-bridge inverter architecture. the resonant operation maximizes striking capability and provides near-sinusoidal waveforms over the entire input range to improve ccfl lifetime. the controller operates over a wide input voltage range of 4.6v to 28v with high power-to-light efficiency. the device also includes safety features that effectively protect against many single-point fault conditions including lamp-out and short-circuit faults. the max8709/max8709a achieve 10:1 dimming range by ?hopping?the lamp current on and off using a digital pulse-width-modulation (dpwm) method. the minimum dpwm duty cycle of the max8709 is 9.375% and the minumum duty cycle of the max8709a is 12.5%. the brightness is controlled with a 2-wire smbus-compati- ble interface. the device directly drives the four external n-channel power mosfets of the full-bridge inverter. an internal 5.3v linear regulator powers the mosfet dri- vers, the dpwm oscillator, and most of the internal cir- cuitry. the max8709/max8709a are available in a space-saving 28-pin thin qfn package and operates over a -40? to +85? temperature range. applications notebook computer displays lcd tvs lcd monitors automotive displays features ? synchronized to resonant frequency longer lamp life guaranteed striking capability high power-to-light efficiency ? wide input voltage range (4.6v to 28v) ? feed forward for excellent line rejection ? smbus dimming control interface ? 10:1 dimming range ? guaranteed 200hz to 220hz dpwm frequency ? secondary voltage limit reduces transformer stress ? adjustable lamp-out protection with 1s timer ? secondary current limit protects against high- voltage short circuits to ground ? small 5mm x 5mm thin qfn package max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ________________________________________________________________ maxim integrated products 1 ordering information scl sda sus cci ccv batt gnd lot ref ilim v cc v dd bst2 bst1 gh1 lx1 lx2 gl1 pgnd gl2 gh2 vfb isec ifb max8709/ max8709a v in minimal operating circuit 19-3177; rev 1; 3/05 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package max8709eti -40? to +85? 28 thin qfn 5mm x 5mm max8709aeti -40? to +85? 28 thin qfn 5mm x 5mm smbus is a trademark of intel corp. pin configuration appears at end of data sheet.
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = 0c to +85c . typical values are at t a = +25?, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. batt to gnd..........................................................-0.3v to +30v bst1, bst2 to gnd ...............................................-0.3v to +36v bst1 to lx1, bst2 to lx2 ........................................-0.3v to +6v gh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) gh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) v cc , v dd to gnd .....................................................-0.3v to +6v ref, ilim to gnd .......................................-0.3v to (v cc + 0.3v) gl1, gl2 to gnd .......................................-0.3v to (v dd + 0.3v) cci, ccv, lot to gnd ............................................-0.3v to +6v ifb, isec, vfb to gnd................................................-6v to +6v sda, scl, sus to gnd............................................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v continuous power dissipation (t a = +70?) 28-pin thin qfn (derate 20.84mw/? above +70?) .. 1667mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units v cc = v dd = v batt 4.6 5.5 v batt input voltage range v cc = v dd = open 5.5 28.0 v v batt = 28v 1.5 3 v batt quiescent current v sus = 5.5v v batt = v cc = 5v 3 ma v batt quiescent current, shutdown sus = gnd 6 20 a v cc output voltage, normal operation v sus = 5.5v, 6v < v batt < 28v, 0 < i load < 20ma 5.0 5.35 5.5 v v cc output voltage, shutdown sus = gnd, no load 3.5 4.6 5.5 v v cc rising (leaving lockout) 4.5 v cc undervoltage-lockout threshold v cc falling (entering lockout) 4.0 v v cc undervoltage-lockout hysteresis 200 mv v cc power-on reset (por) threshold rising edge 0.90 1.75 2.70 v v cc por hysteresis 50 mv ref output voltage, normal operation 4.5v < v cc < 5.5v, i load = 40? 1.96 2.00 2.04 v gh1, gh2, gl1, gl2 on-resistance i test = 100ma, v cc = v dd = 5.3v 9 18 ? gh1, gh2, gl1, gl2 output current 0.5 a bst1, bst2 leakage current v bst _ = 12v, v lx _ = 7v 5 a input resonant frequency guaranteed by design 25 300 khz minimum off-time 180 280 380 ns maximum off-time 18 28 38 ? current-limit threshold lx1 - gnd, lx2 - gnd (fixed) ilim = v cc 180 200 220 mv v ilim = 0.5v 80 100 120 current-limit threshold lx1 - gnd, lx2 - gnd (adjustable) v ilim = 2.0v 370 400 430 mv minimum current threshold lx1 - gnd, lx2 - gnd 6mv
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = 0c to +85c . typical values are at t a = +25?, unless otherwise noted.) parameter conditions min typ max units lot input voltage range 0.5 v ref v lot input bias current -2 +2 ? ifb input voltage range -1.7 +1.7 v ifb regulation point 380 400 420 mv ifb input bias current v ifb = 0.4v -2 +2 ? ifb lamp-out threshold lot = ref 500 600 700 mv ifb to cci transconductance 1v < v cci < 2.5v 100 ? cci output impedance 20 m ? isec input voltage range -2 +2 v isec regulation threshold 1.20 1.25 1.30 v isec input bias current v isec = 1.25v -2 +2 ? vfb input voltage range -2 +2 v vfb input bias current v vfb = 0.5v -0.5 +0.5 ? vfb regulation point 490 510 530 mv vfb to ccv transconductance 1v < v ccv < 2.7v 40 ? vfb zero-voltage crossing threshold -10 +10 mv ccv output impedance 20 m ? max8709 200 210 220 digital pwm chopping frequency max8709a 204 210 216 hz lamp-out detection timeout timer v ifb < 0.1v (note 1) 1.14 1.22 1.30 s sda, scl, sus input low voltage 0.8 v sda, scl, sus input high voltage 2.1 v sda, scl, sus input hysteresis 300 mv sda, scl, sus input bias current -1 +1 ? sda output low sink current v sda = 0.4v 4 ma scl serial clock high period t high 4s scl serial clock low period t low 4.7 ? start-condition setup time t su:sta 4.7 ? start-condition hold time t hd:sta 4s sda valid to scl rising-edge setup time, slave clocking-in data t su:dat 250 ns scl falling edge to sda transition t hd:dat 0ns scl falling edge to sda valid, reading out data t dv 700 ns
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 4 _______________________________________________________________________________________ electrical characteristics (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = -40c to +85c . typical values are at t a = +25?, unless otherwise noted.) (note 2) parameter conditions min typ max units v cc = v dd = v batt 4.6 5.5 v batt input voltage range v cc = v dd = open 5.5 28.0 v v batt = 28v 3 v batt quiescent current v sus = 5.5v v batt = v cc = 5v 3 ma v batt quiescent current, shutdown sus = gnd 20 ? v cc output voltage, normal operation v sus = 5.5v, 6v < v batt < 28v, 0 < i load < 20ma 5.0 5.5 v v cc output voltage, shutdown sus = gnd, no load 3.5 5.5 v v cc rising (leaving lockout) 4.5 v cc undervoltage-lockout threshold v cc falling (entering lockout) 4.0 v v cc power-on reset (por) threshold rising edge 0.90 2.70 v ref output voltage, normal operation 4.5v < v cc < 5.5v, i load = 40? 1.95 2.05 v gh1, gh2, gl1, gl2 on-resistance i test = 100ma, v cc = v dd = 5.3v 18 ? bst1, bst2 leakage current v bst _ = 12v, v lx _ = 7v 5 a input resonant frequency guaranteed by design 25 300 khz minimum off-time 180 380 ns maximum off-time 18 38 ? current-limit threshold lx1 - gnd, lx2 - gnd (fixed) ilim = v cc 180 220 mv v ilim = 0.5v 80 120 current-limit threshold lx1 - gnd, lx2 - gnd (adjustable) v ilim = 2.0v 370 430 mv current-limit leading-edge blanking 250 450 ns lot input voltage range 0.5 v ref v lot input bias current -2 +2 ? ifb input voltage range -1.7 +1.7 v ifb regulation point 380 420 mv ifb input bias current v ifb = 0.4v -2 +2 ? ifb lamp-out threshold lot = ref 500 700 mv isec input voltage range -2 +2 v isec regulation point 1.20 1.30 v isec input bias current v isec = 1.25v -2 +2 ? vfb input voltage range -2 +2 v vfb input bias current v vfb = 0.5v -0.5 +0.5 ? vfb regulation point 490 530 mv vfb zero-voltage crossing threshold -10 +10 mv max8709 200 220 digital pwm chopping frequency max8709a 204 216 hz
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = -40c to +85c . typical values are at t a = +25?, unless otherwise noted.) (note 2) parameter conditions min typ max units lamp-out detection timeout timer v ifb < 0.1v (note 1) 1.14 1.30 s sda, scl, sus input low voltage 0.8 v sda, scl, sus input high voltage 2.1 v sda, scl, sus input bias current -1 +1 ? sda output low sink current v sda = 0.4v 4 ma scl serial clock high period t high 4s scl serial clock low period t low 4.7 ? start-condition setup time t su:sta 4.7 ? start-condition hold time t hd:sta 4s sda valid to scl rising-edge setup time, slave clocking-in data t su:dat 250 ns scl falling edge to sda transition t hd:dat 0ns note 1: corresponds to 256 dpwm cycles. note 2: specifications to -40? are guaranteed by design based on final characterization results. t ypical operating characteristics (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = +25?, unless otherwise noted.) low input-voltage operation (v batt = 8v) max8709 toc01 a: v ifb , 2v/div b: v vfb , 2v/div c: v lx1 , 10v/div d: v lx2 , 10v/div 10 s/div 0v 0v 0v a b c d 0v high input-voltage operation (v batt = 20v) max8709 toc02 a: v ifb , 2v/div b: v vfb , 2v/div c: v lx1 , 10v/div d: v lx2 , 10v/div 10 s/div 0v 0v 0v a b c d 0v line-transient response max8709 toc03 a: v batt , 5v/div b: v ifb , 2v/div c: v vfb , 2v/div d: v lx1 , 10v/div 40 s/div 0v 0v 8v a b c d 0v
lamp-out voltage limiting and timeout max8709 toc09 a: v vfb , 1v/div b: v ifb , 1v/div 0v 0v a b 200ms/div max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = +25?, unless otherwise noted.) startup max8709 toc04 a: v sus , 5v/div b: v ifb , 2v/div c: v vfb , 2v/div d: v lx1 , 10v/div 2ms/div 0v 0v 0v a b c d 0v dpwm operation (10%) max8709 toc05 a: v ccv , 200mv/div b: v ifb , 1v/div c: v vfb , 1v/div 1ms/div 0v 0v 1.2v a b c dpwm operation (50%) max8709 toc06 a: v ccv , 200mv/div b: v ifb , 1v/div c: v vfb , 1v/div 1ms/div 0v 0v 1.2v a b c dpwm soft-start max8709 toc07 a: v ifb , 1v/div b: v vfb , 1v/div 40 s/div 0v 0v 1.2v a b cci ccv dpwm soft-stop max8709 toc08 a: v ifb , 1v/div b: v vfb , 1v/div 40 s/div 0v 0v a b cci ccv
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface _______________________________________________________________________________________ 7 switching frequency vs. input voltage max8709 toc10 input voltage (v) switching frequency (khz) 22 19 16 13 10 50 54 58 62 46 725 dpwm frequency vs. input voltage max8709 toc11 input voltage (v) dpwm frequency (hz) 22 19 16 13 10 205 210 215 220 200 725 electrical efficiency vs. input voltage max8709 toc12 input voltage (v) electrical efficiency (%) 22 19 16 13 10 60 70 80 90 100 50 725 normalized rms lamp current vs. input voltage max8709 toc13 input voltage (v) rms lamp-current error (%) 22 19 10 13 16 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 -0.8 725 -0.15 -0.10 0 -0.05 0.05 0.10 040 20 60 80 100 ref load regulation max8709 toc14 ref load current ( a) ref voltage error (%) 0 20 60 40 80 100 0812 4162 0242832 normalized brightness vs. brightness code max8709 toc15 brightness code normalized brightness (%) normalized v cc line regulation max8709 toc16 input voltage (v) v cc voltage error (%) 20 15 10 -0.8 -0.6 -0.4 -0.2 0 0.2 -1.0 525 v cc = 5.3v v cc load regulation max8709 toc17 v cc voltage error (%) 16 12 8 4 -1.2 -0.9 -0.6 -0.3 0 -1.5 020 external load current (ma) t ypical operating characteristics (continued) (circuit of figure 1. v batt = 12v, v lot = v ref , v cc = v dd, v sus = 5.3v, t a = +25?, unless otherwise noted.) ref output vs. temperature max8709 toc18 temperature ( c) ref voltage error (%) 80 60 40 20 0 -20 -0.20 -0.15 -0.10 -0.05 0 0.05 -0.25 -40 100
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 8 _______________________________________________________________________________________ pin description pin name function 1 ilim current-limit threshold adjustment. connect a resistive voltage-divider between ref or v cc and gnd. the current-limit threshold measured between lx_ and gnd is 1/5th the voltage forced at ilim. the ilim adjustment range is 0 to 3v. connect ilim to v cc to select the default current-limit threshold of 0.2v. 2 ref 2v reference output. bypass ref to gnd with a 0.1? ceramic capacitor. ref is discharged to gnd during shutdown. 3 lot lamp-out threshold adjustment. the lamp-out threshold is 30% of the voltage at lot. the lot adjustment range is from 0.5v to v ref . 4 gnd analog ground. the ground return for v cc , ref, and other analog circuitry. connect gnd to pgnd under the ic at the ic? backside exposed metal pad. 5 isec secondary current-limit sense input. the secondary current limit controls the transformer secondary current even if the ifb sense resistor is shorted. see the secondary current limit (isec) section. 6 sda smbus serial data input 7 scl smbus serial clock input 8 sus smbus suspend input 9, 10, 11, 23 n.c. no connection. not internally connected. 12 v dd gate-driver supply input. connect v dd to v cc , the output of the linear regulator. bypass v dd with a 0.1? capacitor to pgnd. 13 pgnd power ground. gate-driver current flows through this pin. 14 gl2 low-side mosfet nl2 gate-driver output 15 gl1 low-side mosfet nl1 gate-driver output 16 gh1 high-side mosfet nh1 gate-driver output 17 lx1 switching node connection. lx1 is the internal gate driver? (gh1?) source connection for the high-side mosfet nh1. lx1 is also the sense input to the current comparators. 18 bst1 driver bootstrap input for high-side mosfet nh1. connect bst1 through a diode to v dd and through a 0.1? capacitor to lx1 (figure 1). 19 bst2 driver bootstrap input for high-side mosfet nh2. connect bst2 through a diode to v dd and through a 0.1? capacitor to lx2 (figure 1). 20 lx2 switching node connection. lx2 is the internal gate driver? (gh2?) source connection for the high-side mosfet nh2. lx2 is also the sense input to the current comparators. 21 gh2 high-side mosfet nh2 gate-driver output 22 vfb lamp output feedback sense input. the average value on vfb is regulated during startup and open- lamp conditions to 0.5v by controlling the on-time of high-side switches. a capacitive voltage-divider between the ccfl lamp output and gnd is sensed to set the maximum average lamp output voltage. 24 ifb lamp current-sense input. the voltage on ifb is used to regulate the lamp current. if the ifb input falls below 30% of the lot voltage for 1.22s, then the max8709/max8709a activate the lamp-out fault latch. 25 cci current-loop compensation pin. cci is the output of the current-loop transconductance amplifier (gmi) that regulates the ccfl current. the cci voltage controls the time interval during which the full bridge applies the input voltage (batt) to the transformer primary. connect cci to gnd through a 0.1? capacitor. cci is internally discharged to gnd in shutdown.
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface _______________________________________________________________________________________ 9 pin description (continued) pin name function 26 ccv voltage-loop compensation pin. ccv is the output of the voltage-loop transconductance amplifier (gmv) that regulates the maximum average secondary transformer voltage. the ccv voltage controls the time interval during which the full bridge applies the input voltage (batt) to the transformer primary. the ccv capacitor also sets the rise time and fall time of the lamp current in dpwm. connect ccv to gnd with a 6.8nf capacitor. ccv is internally discharged to gnd in shutdown. 27 batt max8709/max8709a supply input. input to the internal 5.3v linear regulator (v cc ) that provides power to the device. bypass batt to gnd with a 0.1? capacitor. 28 v cc 5.3v linear-regulator output. v cc is the supply voltage for the max8709/max8709a. bypass v cc to gnd with a 0.47? ceramic capacitor. v cc can also be connected to batt if v batt < 5.5v. v in 7v to 24v c8 0.1 f r4 100k ? c9 0.1 f r5 100k ? c10 0.01 f c11 0.1 f smbsus smbdata smbclk scl sda sus cci ccv batt gnd lot ref ilim v cc v dd bst2 bst1 gh1 lx1 lx2 gl1 pgnd gl2 gh2 vfb isec ifb max8709/ max8709a d1 c7 0.47 f c5 0.1 f c6 0.1 f c1 4.7 f 25v nh1 nl1 nh2 nl2 c2 1 f t1 1:93 ccfl c3 15pf 3kv r3 40.2 ? 1% c4 22nf r2 2k ? r1 150 ? 1% figure 1. typical operating circuit of the max8709/max8709a
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 10 ______________________________________________________________________________________ smbus interface brightness dac dpwm osc ramp generator peak detector supply control logic mux lamp-out comp gmv gmi ccv clamp pk_det clamp imin comp imax comp lx1 lx2 0.5v 0.4v 6mv 400 a sec oc comp pwm comp dpwm comp 1.25v max8709 max8709a sus sda scl lot ref ccv cci ilim ref ifb vfb batt gnd bst1 gh1 lx1 bst2 gh2 lx2 gl1 v dd gl2 pgnd isec ref v cc vin ccfl figure 2. max8709/max8709a functional diagram
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 11 t ypical operating circuit the typical operating circuit of the max8709/ max8709a ( figure 1) is a complete ccfl backlight inverter for notebook tft lcd panels. the circuit works over an input voltage range of 7v to 24v with an rms lamp current of 6ma. the circuit? maximum rms open-lamp voltage is limited to 1600v. table 1 lists rec- ommended component options, and table 2 lists the component suppliers?contact information. detailed description the max8709/max8709a control a full-bridge resonant inverter to convert an unregulated dc input into a near- sinusoidal ac output for powering ccfls. the lamp brightness is adjusted by turning the lamp on and off with an internal dpwm signal. the duty cycle of the dpwm signal is set through an smbus-compatible 2- wire serial interface. figure 2 shows the functional dia- gram of the max8709/max8709a. resonant operation the max8709/max8709a drive the four n-channel power mosfets that make up the zero-voltage-switching (zvs) full-bridge inverter as shown in figure 3. assume that nh1 and nl2 are turned on at the beginning of a switch- ing cycle as shown in figure 3(a). the primary current flows through mosfet nh1, dc blocking cap c2, the primary side of transformer t1, and mosfet nl2. during this interval, the primary current ramps up until the con- troller turns off nh1. when nh1 turns off, the primary cur- rent forward biases the body diode of nl1, which clamps the lx1 voltage just below ground as shown in figure 3(b). when the controller turns on nl1, its drain-to-source voltage is near zero because its forward-biased body diode clamps the drain. since nl2 is still on, the primary current flows through nl1, c2, the primary side of t1, and nl2. once the primary current drops to the minimum current threshold (6mv / r ds(on) ), the controller turns off nl2. the remaining energy in t1 charges up the lx2 table 1. component list designation description c1 4.7? ?0%, 25v x5r ceramic capacitor (1210) murata grm32rr61e475k taiyo yuden tmk325bj475mn tdk c3225x7r1e475m c2 1? ?0%, 25v x7r ceramic capacitor (1206) murata grm31mr71e105k taiyo yuden tmk316bj105kl tdk c3216x7r1e105k c3 15pf ?pf, 3kvhigh-voltage ceramic capacitor (1808) murata grm42d1x3f150j tdk c4520c0g3f150f c4 0.022? ?0%, 16v x7r ceramic capacitor (0402) murata grp155r71c223k taiyo yuden emk105bj223kv tdk c1005x7r1c223k c5, c6, c8, c9 0.1? ?0%, 25v x7r ceramic capacitors (0603) murata grm188r71e104k taiyo yuden tmk107bj104ka tdk c1608x7r1e104k designation description c7 0.47? ?0%, 10v x5r ceramic capacitor (0603) taiyo yuden lmk107bj474ka tdk c1608x5r1a474k d1 dual silicon switching diode, common anode (sot-323) central semiconductor cmsd2836 diodes incorporated baw56w nh1/2, nl1/2 30v, 0.095 dual n-channel mosfets (6-pin sot23) fairchild fdc6561an r1 150 ? ?% resistor (0603) r2 2k ? ?% resistor (0603) r3 39 ? ?% (resistor (0603) r4, r5 100k ? ?% resistors (0603) t1 ccfl transformer, 1:93 turns ratio sumida 5371-400-w1423 toko t912mg-1018 table 2. component suppliers supplier website central semiconductor www.centralsemi.com fairchild semiconductor www.fairchildsemi.com murata www.murata.com sumida www.sumida.com taiyo yuden www.t-yuden.com tdk www.components.tdk.com
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 12 ______________________________________________________________________________________ node until the body diode of nh2 is forward biased. when nh2 turns on, it does so with near-zero drain-to- source voltage. the primary current reverses polarity as shown in figure 3(c), beginning a new cycle with the cur- rent flowing in the opposite direction, with nh2 and nl1 on. the primary current ramps up until the controller turns off nh2. when nh2 turns off, the primary current forward biases the body diode of nl2, which clamps the lx2 volt- age just below ground as shown in figure 3(d). after the lx2 node goes low, the controller losslessly turns on nl2. once the primary current drops to the minimum current threshold, the controller turns off nl1. the remaining energy charges up the lx1 node until the body diode of nh1 is forward biased. finally, nh1 losslessly turns on, beginning a new cycle as shown in figure 3(a). note that switching transitions on all four power mosfets occur under zvs conditions, which reduce transient power loss- es and emi. the simplified ccfl inverter circuit is shown in figure 4(a). the full-bridge power stage is simplified and rep- resented as a square-wave ac source. the resonant tank circuit can be further simplified to figure 4(b) by removing the transformer. c s is the primary series capacitor, c s is the series capacitance reflected to the secondary, c p is the secondary parallel capacitor, n is the transformer turns ratio, l is the transformer sec- t1 c2 vbatt (a) nh1 on nl1 off nh2 off nl2 on lx2 lx1 t1 c2 vbatt (b) nh1 off nl1 on nh2 off nl2 on lx2 lx1 t1 c2 vbatt (c) nh1 off nl1 on nh2 on nl2 off lx2 lx1 t1 c2 vbatt (d) nh1 off nl1 on nh2 off nl2 on lx2 lx1 (body diode turns on first) (body diode turns on first) figure 3. resonant operation
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 13 ondary leakage inductance, and r l is an idealized resistance that models the ccfl in normal operation. figure 5 shows the frequency response of the resonant tank? voltage gain under different load conditions. the primary series capacitor is 1?, the secondary parallel capacitor is 15pf, the transformer turns ratio is 1:93, and the secondary leakage inductance is 260mh. notice there are two peaks, f s and f p , in the frequency response. the first peak, f s , is the series resonant peak determined by the reflected series capacitor and the secondary leakage inductance: the second peak, f p , is the parallel resonant peak deter- mined by the reflected series capacitor, the parallel capacitor, and the secondary leakage inductance: these two frequencies set the lower and upper bound- aries of resonant operation. when the lamp is off, the operating point of the resonant tank is close to the paral- lel resonant peak due to the infinite lamp impedance. the circuit displays the characteristics of a parallel- loaded resonant converter, acting like a voltage source to generate the necessary striking voltage. theoretically, the output voltage of the resonant converter keeps going until the lamp is ionized. once the lamp is ionized, the equivalent load resistance decreases rapidly and the operating point moves toward the series resonant peak. the series resonant operation causes the circuit to behave like a current source. current and voltage control loops (cci, ccv) the max8709/max8709a use a current loop and a voltage loop to control the power delivered to the ccfl. the current loop is the dominant loop in regulat- ing the lamp current. the voltage loop limits the trans- former secondary voltage and is active during startup, the dpwm off-time, and open-lamp fault. both the current and the voltage loops use transcon- ductance error amplifiers for regulation. the ac lamp current is measured with a sense resistor in series with the ccfl. the voltage across this resistor is applied to the ifb input and is internally half-wave rectified. the current-loop transconductance error amplifier com- pares the rectified ifb voltage with a 400mv internal threshold to create an error current. the error current charges and discharges a capacitor connected between cci and ground to generate an error voltage v cci . similarly, the ac voltage across the transformer secondary winding is measured through a capacitive voltage-divider. the sense voltage is applied to the vfb input and is internally half-wave rectified. the volt- f l cc cc p sp sp ' ' = + 1 2 f lc s s = 1 2 ' ac source ccfl c p l c s 1:n (a) ac source r l c p l c' s = (b) c s n 2 figure 4. equivalent resonant tank circuit frequency (khz) voltage gain (v/v) 80 60 40 20 1 2 3 4 0 0 100 r l increasing figure 5. frequency response of the resonant tank
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 14 ______________________________________________________________________________________ age-loop transconductance error amplifier compares the rectified vfb voltage with a 500mv internal thresh- old to create an error current. the error current charges and discharges a capacitor connected between ccv and ground to generate an error voltage v ccv . the lower of v cci and v ccv takes control and is compared with an internal ramp signal to set the high-side mosfet switch on-time (t on ). lamp startup a ccfl is a gas discharge lamp that is normally driven in the avalanche mode. to start ionization in a nonion- ized lamp, the applied voltage (striking voltage) must be increased to the level required for the start of avalanche. the striking voltage can be several times the typical operating voltage. because of the resonant topology, the striking voltage is guaranteed regardless of the temperature. before the lamp is ionized, the lamp impedance is infinite. the transformer secondary leakage inductance and the high-voltage parallel capacitor determine the unloaded resonant frequency. since the unloaded resonant cir- cuit has a high q, it is easy to generate high voltages across the lamp. operation during startup differs from the steady-state condition described in the current and voltage control loops section. upon power-up, v cci slowly rises, increasing the duty cycle, which provides soft-start. during this time, v ccv is limited to 150mv above v cci . once the secondary voltage reaches the strike voltage, the lamp current begins to increase. when the lamp current reaches the regulation point, v cci exceeds v ccv and it reaches steady state. feed-forward control and dropout operation the max8709/max8709a are designed to maintain tight control of the transformer secondary under all transient conditions including dropout. the feed-for- ward control instantaneously adjusts the t on time for changes in input voltage (v batt ). this feature provides immunity to input voltage variations and simplifies loop compensation over wide input voltage ranges. the feed-forward control also improves the line regulation for short dpwm on-times and makes startup transients less dependent on the input voltage. feed-forward control is implemented by increasing the pwm? internal voltage ramp rate for higher v batt . this has the effect of varying t on as a function of the input voltage while maintaining about the same signal levels at v cci and v ccv . since the required voltage change across the compensation capacitors is minimal, the controller? response to input voltage changes is essentially instantaneous. to maximize run time, it may be desirable to allow the circuit to operate in dropout if the backlight? perfor- mance is not critical. when v batt is very low, the con- troller loses current regulation and runs at maximum duty cycle. under these circumstances, a transient overvoltage condition could occur when the ac adapter is suddenly applied to power the circuit. the feed-forward circuitry minimizes variations in lamp volt- age due to such input voltage steps. the regulator also clamps the voltage on v cci . these two features togeth- er ensure that overvoltage transients do not appear on the transformer when leaving dropout. the v cci clamp is unique in that it limits v cci to the peak voltage of the pwm ramp. as the circuit reaches dropout, v cci approaches the pwm ramp? peak in order to reach maximum t on . if v batt decreases fur- ther, the control loop loses regulation and v cci tries to reach its positive supply rail. the clamp on v cci pre- vents this from happening and v cci rides just above the pwm ramp? peak. if v batt continues to decrease, the feed-forward control reduces the amplitude of the pwm ramp and the clamp pulls v cci down. when v batt suddenly steps out of dropout, v cci is still low and maintains the drive on the transformer at the old dropout level. the control loop then slowly corrects and increases v cci to bring the circuit back into regulation. dpwm dimming control the max8709/max8709a control the brightness of the ccfl by ?hopping?the lamp current on and off using an internal dpwm signal. the frequency of the dpwm signal is 210hz. the brightness code set through the smbus interface determines the duty cycle of the dpwm signal. a brightness code of 0b00000 corresponds to a 9.375% dpwm duty cycle for max8709, and a 12.5% duty cycle for max8709a. a brightness code of 0b11111 corre- sponds to a 100% dpwm duty cycle. the duty cycle changes by 3.125% per step, but codes 0b00000 to 0b00010 all produce 9.375% for max8709 as shown in figure 6. codes 0b00000 to 0b00011 all produce 12.5% for max8709a. in dpwm operation, the cci and ccv control loops work together to regulate the lamp current, limit the secondary voltage, and control the rising and falling of the lamp cur- rent. during the dpwm off-cycle, the output of the volt- age-loop error amplifier (ccv) is set to 1.15v and the current-loop error-amplifier output (cci) is high imped- ance. the high-impedance output acts like a sample- and-hold circuit to keep v cci from changing during the off-cycles. at the beginning of the dpwm on-cycle, v ccv
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 15 linearly rises, gradually increasing t on , which provides soft-start. once v ccv exceeds v cci , the current-loop error amplifier takes control and starts to regulate the lamp current. in the meantime, v ccv continues to rise and is limited to 150mv above v cci . at the end of the dpwm on-cycle, the ccv capacitor discharges linearly, gradually decreasing t on and providing soft-stop. por and uvlo the max8709/max8709a include power-on-reset (por) and undervoltage-lockout (uvlo) circuits. the por resets all internal registers such as dac outputs, fault latches, and all smbus registers. por occurs when v cc is below 1.5v. the smbus input logic thresh- olds are only guaranteed to meet electrical characteris- tic limits for v cc as low as 3.5v, but the interface continues to function down to the por threshold. the uvlo is activated and disables both high-side and low-side switch drivers when v cc is below 4.2v (typ). low-power shutdown (sus) when the max8709/max8709a are placed in shut- down, all functions of the ic are turned off except for the 5.3v linear regulator that powers all internal regis- ters and the smbus interface. the smbus interface is accessible in shutdown. in shutdown, the linear-regula- tor output voltage drops to about 4.5v and the supply current is 6a (typ), which is the required power to maintain all internal register states. while in shutdown, lamp-out detection and short-circuit detection latches are reset. the device can be placed into shutdown either by writing to the shutdown-mode register or pulling sus low. lamp-out protection for safety, the max8709/max8709a monitor the lamp- current feedback (ifb) to detect faulty or open ccfl tubes and secondary short circuits in the lamp and ifb sense resistor. if the voltage on ifb is continuously below 30% of the lot voltage for greater than 1.22s (typ), the max8709/max8709a latch off the full bridge. unlike the normal shutdown mode, the linear-regulator output (v cc ) remains at 5.3v. toggling sus or cycling the input power reactivates the device. during the 1.22s delay, v cci slowly rises, increasing t on in an attempt to maintain lamp current regulation. as v cci rises, v ccv rises with it until the secondary voltage reaches its preset limit. at this point, v ccv stops and limits the secondary voltage by limiting t on . because v ccv is limited to 150mv above v cci , the volt- age control loop is able to quickly limit the secondary voltage. without this clamping feature, the transformer voltage overshoots to dangerous levels because v ccv takes time to slew down from its supply rail. primary overcurrent protection (ilim) the max8709/max8709a sense primary current in each switching cycle. when the regulator turns on the low-side mosfet, a comparator monitors the voltage drop from lx_ to gnd. if the voltage exceeds the current-limit threshold, the regulator turns off the high-side switch at the opposite side of the primary to prevent the trans- former primary current from increasing further. the current-limit threshold can be adjusted using the ilim input. connect a resistive voltage-divider between ref or v cc and gnd with the midpoint connected to ilim. the current-limit threshold measured between lx_ and gnd is 1/5th the voltage at ilim. the ilim adjustment range is 0 to 3v. connect ilim to v cc to select the default current-limit threshold of 0.2v. secondary current limit (isec) the secondary current limit provides failsafe current limiting in case a failure, such as a short circuit or leak- age from the lamp high-voltage terminal to ground, pre- vents the cci current control loop from functioning properly. isec monitors the voltage across a sense resistor placed between the transformer? low-voltage secondary terminal and ground. the isec voltage is internally half-wave rectified and continuously com- pared to the isec regulation threshold (1.25v typ). any time the isec voltage exceeds the threshold, a con- trolled current is drawn from cci to reduce the on-time of the bridge? high-side switches. reference output (ref) the reference output is nominally 2v, and can source at least 40? (see the typical operating characteristics ). 0 10 20 30 60 70 40 50 80 90 100 012 48 20 16 24 28 32 brightness code dpwm duty cycle (%) dpwm settings figure 6. dpwm settings
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 16 ______________________________________________________________________________________ bypass ref with a 0.22? ceramic capacitor connected between ref and gnd. linear-regulator output (v cc ) the internal linear regulator steps down the dc input volt- age to 5.3v (typ). the linear regulator supplies power to the internal control circuitry of the max8709/max8709a and can also be used to power the mosfet drivers by connecting v cc directly to v dd . the v cc voltage drops to 4.5v in shutdown. smbus interface (sda, scl) the max8709/max8709a support an intel smbus-com- patible 2-wire digital interface. sda is the bidirectional data line and scl is the clock line of the 2-wire interface corresponding respectively to smbdata and smbclk lines of the smbus. sda and scl are schmidt-triggered inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. the max8709/max8709a use the write-byte, read-byte, and receive-byte protocols ( figure 7). the smbus protocols are documented in system management bus specification v1.1 and are available at http://www.smbus.org/. the max8709/max8709a are slave-only devices and respond to the 7-bit address 0b01011000 (i.e., with the r/ w bit clear indicating a write, this corresponds to 0x58). the max8709/max8709a have three functional registers: a 5-bit brightness register (bright4?right0), a 3-bit shutdown-mode register (shmd2?hmde0), and a 2-bit status register (status1?tatus0). in addition, the device has three identification (id) registers: an 8-bit chip id register, an 8-bit chip revision register, and an 8-bit manufacturer id register. communication starts with the master signaling the beginning of a transmission with a start condition, which is a high-to-low transition on sda while scl is high. when the master has finished communicating with the slave, the master issues a stop condition, which is a low-to-high transition on sda while scl is high. the bus is then free for another transmission. figures 8 and 9 show the timing diagrams for signals on the 2-wire interface. the address byte, command byte, and data byte are transmitted between the start and stop con- ditions. the sda state is allowed to change only while scl is low, except for the start and stop conditions. data is transmitted in 8-bit words and is sampled on the 1b ack 1b 7 bits address ack 1b wr 8 bits data 1b ack p 8 bits s command write-byte format receive-byte format slave address command byte: selects which register you are writing to data byte: data goes into the register set by the command byte 1b ack 1b 7 bits address ack 1b wr s 1b ack 8 bits data 7 bits address 1b rd 1b 8 bits /// p s command slave address slave address command byte: sends command with no data; usually used for one- shot command command byte: selects which register you are reading from slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte 1b ack 7 bits address 1b rd 8 bits data 1b /// p s data byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission wr = write = 0 p = stop condition ack= acknowledged = 0 rd = read =1 /// = not acknowledged = 1 1b ack 7 bits address 1b wr 8 bits command 1b ack p s send-byte format read-byte format figure 7. smbus protocols
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 17 rising edge of scl. nine clock cycles are required to transfer each byte in or out of the max8709/max8709a since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. if the max8709/max8709a receive the correct slave address followed by r/ w = 0, it expects to receive 1 or 2 bytes of information (depending on the protocol). if the device detects a start or stop condition prior to clocking in the bytes of data, it considers this an error condition and disregards all of the data. if the transmission is completed correctly, the registers are updated immediately after a stop (or restart) condition. if the max8709/max8709a receives its cor- rect slave address followed by r/ w = 1, it expects to clock out the register data selected by the previous com- mand byte. smbus commands the max8709/max8709a registers are accessible through several different redundant commands (i.e., the command byte in the read-byte and write-byte pro- tocols), which can be used to read or write the bright- ness, shmd, status, or id registers. table 3 summarizes the command byte? register assignments, as well as each register? power-on state. smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls smbdata line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition figure 8. smbus write timing smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave ab cd e fg h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = acknowledge clock pulse j = stop condition k = new start condition figure 9. smbus read timing
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 18 ______________________________________________________________________________________ the max8709/max8709a also support the receive-byte protocol for quicker data transfers. this protocol accesses the register configuration pointed to by the last command byte. immediately after power-up, the data byte returned by the receive-byte protocol is the inverted contents of the brightness register, left justified (i.e., bright4 is in the most-significant-bit position of the data byte) with the 3 remaining bits containing a one, status1 , and status0 . this gives the same result as using the read-word protocol with 0b10xxxxxx (0xaa and 0xa9) command. use caution with the shorter protocols in multimaster systems, since a second master could overwrite the command byte without informing the first master. during shutdown the serial interface remains fully functional. table 3. commands description data register bit assignment smbus protocol command byte* por state bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) read and write 0x01 0b0xxx xx01 0x17 0 0 0 bright4 (msb) bright3 bright2 bright1 bright0 (lsb) read and write 0x02 0b0xxx xx10 0xf9 status1 status0 111 shmd2 shmd1 shmd0 read only 0x03 0b0xxx xx11 0x0c chipid7 0 chipid6 0 chipid5 0 chipid4 0 chipid3 1 chipid2 1 chipid1 0 chipid0 1 read only 0x04 0b0xxx xx00 0x00 chiprev7 0 chiprev6 0 chiprev5 0 chiprev4 0 chiprev3 0 chiprev2 0 chiprev1 0 chiprev0 0 read and write 0xaa 0b10xx xxx0 0x40 bright4 (msb) bright3 bright2 bright1 bright0 (lsb) 0 status1 status0 read and write 0xa9 0b10xx xxx1 0x40 bright4 (msb) bright3 bright2 bright1 bright0 (lsb) 0 status1 status0 read only 0xfe 0b11xx xxx0 0x4d mfgid7 0 mfgid6 1 mfgid5 0 mfgid4 0 mfgid3 1 mfgid2 1 mfgid1 0 mfgid0 1 read only 0xff 0b11xx xxx1 0x0c chipid7 0 chipid6 0 chipid5 0 chipid4 0 chipid3 1 chipid2 1 chipid1 0 chipid0 1 * the hexadecimal command byte shown is recommended for maximum forward compatibility with future products. x = don? care. table 4. shmd register bit descriptions bit name por state description 2 shmd2 0 shmd2 = 1 forces the lamp off and sets status1. shmd2 = 0 allows the lamp to operate, although it may still be shut down by sus (depending on the state of shmd1 and shmd0). 1 shmd1 0 when sus = 0, this bit has no effect. sus = 1 and shmd1 = 1 forces the lamp off and sets status1. sus = 1 and shmd1 = 0 allows the lamp to operate, although it may still be shut down by the shmd2 bit. 0 shmd0 1 when sus = 1, this bit has no effect. sus = 0 and shmd0 = 1 forces the lamp off and sets status1. sus = 0 and shmd0 = 0 allows the lamp to operate, although it may still be shut down by the shmd2 bit.
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 19 brightness register [bright4 ?bright0] (por = 0b10111) the 5-bit brightness register corresponds to the 5-bit brightness code used in dimming control (see the dimming control section). bright4 - bright0 = 0b11111 sets minimum brightness and bright4 - bright0 = 0b00000 sets maximum brightness. note that the brightness-register polarity of command bytes 0xa9 and 0xaa are inverted from that of command byte 0x01. shutdown-mode register [shmd2?hmd0] (por = 0b001) the 3-bit shutdown-mode register configures the oper- ation of the device when the sus pin is toggled as described in table 4. the shutdown-mode register can also be used to directly shut off the ccfl regardless of the state of sus ( table 5). status register [status1?tatus0] (por = 0b11) the status register returns information on fault condi- tions. if the max8709/max8709a detect that v ifb does not exceed 30% of v lot continuously for 1.22s, the ic latches status1 to zero. status1 is reset to 1 by tog- gling sus or by toggling the input power. status0 reports 1 as long as no overcurrent condi- tions are detected. if an overcurrent condition is detect- ed in any given digital pwm period, status0 is cleared for the duration of the following digital pwm period. if an overcurrent condition is not detected in any given digital pwm period, status0 is set for the duration of the following digital pwm period. note that the status-register polarity of command bytes 0xa9 and 0xaa are inverted from that of command byte 0x02. id registers the id registers return information on the manufacturer chip id and the chip revision number. the max8709/max8709a are the first-generation advanced ccfl controller and its chiprev is 0x00. reading from mfgid register returns 0x4d, which is the ascii code for m (for maxim). the chipid register returns 0x0d. writing to these registers has no effect. applications information to select the correct component values for the max8709/max8709a, several ccfl parameters must be specified. (table 7) mosfets the max8709/max8709a require four external n-channel power mosfets (nl1, nl2, nh1, and nh2) to form a full-bridge inverter circuit to drive the transformer primary. the regulator senses the on-state drain-to-source voltage of the two low-side mosfets nl1 and nl2 to detect the transformer primary current, so the r ds(on) of nl1 and nl2 should be matched. for instance, if dual mosfets are used to form the full bridge, nl1 and nl2 should be in one package. select dual logic-level n-channel mosfets with low r ds(on) to minimize conduction loss for nl1/nl2 and nh1/nh2. the regulator utilizes the energy stored in the transformer? primary leakage induc- tance to softly turn on each of four switches in the full bridge zero voltage switching (zvs) occurs when the external power mosfets are turned on when their respective drain-to-source voltages are near 0v. zvs effectively eliminates the instantaneous turn-on loss of mosfets caused by c oss (drain-to-source capaci- tance) and parasitic capacitance discharge, and improves efficiency and reduces switching-related emi. table 5. sus and shmd register truth table sus shmd2 shmd1 shmd0 operating mode 00 x0 operate 00x1 shutdown, status1 set 10 0x operate 101x shutdown, status1 set x1xx shutdown, status1 set x = don? care. table 6. status-register bit descriptions (read only, writes have no effect) bit name por state description 1 status1 1 status1 = 0 (or status1 = 1) means that a lamp-out condition has been detected. the status1 bit stays clear even after the lamp-out condition has gone away. the only way to set status1 is to shut off the lamp by programming the shutdown-mode register or by toggling sus. 0 status0 1 status0 = 0 (or status0 = 1) means that an overcurrent condition was detected during the previous digital pwm period. status0 = 1 means that an overcurrent condition was not detected during the previous digital pwm period.
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 20 ______________________________________________________________________________________ setting the lamp current the max8709/max8709a sense the lamp current flow- ing through a resistor r1 ( figure 1) connected between the low-voltage terminal of the lamp and ground. the voltage across r1 is fed to ifb and is internally recti- fied. the max8709/max8709a control the desired lamp current by regulating the average of the half-wave rectified ifb voltage. to set the rms lamp current, determine r1 as follows: where i lamp(rms) is the desired rms lamp current and 400mv is the typical value of the ifb regulation point specified in the electrical characteristics table . to set the rms lamp current to 6ma, the value of r1 should be 148 ? . the closest standard 1% resistors are 147 ? and 150 ? . the precise shape of the lamp-current waveform, which is dependent on lamp parasitics, influ- ences the actual rms lamp current. use a true rms current meter to make final adjustments to r1. setting the secondary voltage limit the max8709/max8709a limit the transformer sec- ondary voltage during lamp striking and lamp-out faults. the secondary voltage is sensed through the capacitive voltage-divider formed by c3 and c4 ( figure 1). the voltage on vfb is proportional to the ccfl voltage. the selection of the parallel resonant capacitor c3 is described in the transformer design and resonant component selection section. c3 is usually between 10pf to 22pf. after the value of c3 is determined, select c4 using the following equation to set the desired maxi- mum rms secondary voltage v lamp(rms) _ max : where 510mv is the typical value of the vfb regulation threshold specified in the electrical characteristics table . if c3 is 15pf, c4 needs to be 21.2nf to set the desired maximum rms secondary voltage to 1600v. the closest standard value of c4 is 22nf. the resistor r2 is used to set the vfb dc bias point to 0v. choose the value of r2 as follows: where f sw is the nominal resonant operating frequency. setting the secondary current limit the max8709/max8709a limit the secondary current even if the ifb sense resistor is shorted or transformer secondary current finds its way to ground without pass- ing through r1. isec monitors the voltage across the sense resistor r3 connected between the low-voltage terminal of the transformer secondary winding and ground. determine the value of r3 using the following equation: where i sec(rms) _ max is the desired maximum rms transformer secondary current during fault conditions, and 1.25v is the typical value of the isec regulation point specified in the electrical characteristics table . transformer design and resonant component selection the transformer is the most important component of the resonant tank circuit. the first step in designing the transformer is to determine the transformer turns ratio. the ratio must be high enough to support the ccfl operating voltage at the minimum supply voltage. the transformer turns-ratio n can be calculated as follows: where v lamp(rms) is the maximum rms lamp voltage in normal operation, and v in(min) is the minimum dc input voltage. the next step in the design procedure is to determine the desired operating frequency range. the max8709/max8709a are synchronized to the natural resonant frequency of the resonant tank. the resonant frequency changes with operating conditions, such as the input voltage, lamp impedance, etc. therefore, the switching frequency varies over a certain range. to ensure reliable operation, the resonant frequency range must be within the operating frequency range specified by the ccfl lamp transformer manufacturers. as dis- cussed in the resonant operation section, the resonant frequency range is determined by the transformer sec- ondary leakage inductance l, the primary series dc- blocking capacitor c2, and the secondary parallel resonant capacitor c3. since it is difficult to control the transformer leakage inductance, the resonant tank design should be based on the existing secondary leakage inductance of the selected ccfl transformer. the leakage inductance values usually have large toler- ance and significant variations among different batch- es. it is best to work directly with transformer vendors n v v lamp rms in min = () () . 09 r v i sec rms max 3 125 2 = . ()_ r fc sw 2 10 24 = c v mv c lamp rms max 4 2 510 13 = ? ? ? ? ? ? ? ? ()_ - r mv i lamp rms 1 400 2 = ()
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 21 on leakage inductance requirements. the max8709/max8709a work best when the secondary leakage inductance is between 250mh and 350mh. the series capacitor c2 sets the minimum operating frequency, which is approximately two times the series resonant peak frequency. choose: where f min is the minimum operating frequency range. the parallel capacitor c3 sets the maximum operating frequency, which is also the parallel resonant peak fre- quency. choose: the transformer core saturation also needs to be con- sidered when selecting the operating frequency. the primary winding should have enough turns to prevent transformer saturation under all operating conditions. use the following expression to calculate the minimum number of turns (n1) of the primary winding: where d max is the maximum duty cycle (approximately 0.8) of the high-side switches, v in(max) is the maximum dc input voltage, b s is the saturation flux density of the core, and s is the minimal cross-section area of the core. compensation design the cci capacitor sets the speed of the current loop that is used during startup, maintaining lamp current regulation, and during transients caused by changing the input voltage. the typical cci value is 0.1?. larger values increase the transient-response delays. smaller values speed up transient response, but extremely small values can cause loop instability. the ccv capacitor sets the speed of the voltage loop that affects soft-start and soft-stop during dpwm opera- tion, and voltage loop stability during startup and open- lamp conditions. the typical ccv capacitor value is 10nf. use the smallest value of ccv that gives an acceptable fault transient response and does not cause excessive ringing at the beginning of a dpwm pulse. n dv bsf max in max smin 1 > () c c flcn max 3 2 42 22 2 ( ) - c n fl min 2 2 22 table 7. ccfl specifications specification symbol units description ccfl minimum striking voltage (kick-off voltage) v strike v rms although ccfls typically operate at less than 550v rms , a higher voltage (1000v rms and up) is required initially to start the tube. the strike voltage is typically higher at cold temperatures and at the end of life of the tube. resonant operation and the high q of the resonant tank generate the required strike voltage of the lamp. ccfl typical operating voltage (lamp voltage) v lamp v rms once a ccfl has been struck, the lamp voltage required to maintain light output falls to approximately 550v rms . short tubes may operate on as little as 250v rms . the operating voltage of the ccfl stays relatively constant, even as the tube? brightness is varied. ccfl operating current (lamp current) i lamp ma rms the desired rms ac current through a ccfl is typically 6ma rms . dc current is not allowed through ccfls. the sense resistor, r1, sets the lamp current. ccfl maximum frequency (lamp frequency) f khz the maximum ac-lamp-current frequency. the circuit should be designed to operate the lamp below this frequency. the max8709/max8709a are designed to operate between 20khz and 100khz.
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface 22 ______________________________________________________________________________________ larger ccv values reduce transient overshoot but can reduce light output at low-dpwm duty cycles by increas- ing the time required to reach the tube strike voltage. other components the external bootstrap circuits formed by d1 and c5/c6 in figure 1 power the high-side mosfet drivers. connect bst1/bst2 through a signal-level silicon diode to v dd , and bypass it to lx1/lx2 with a 0.1? ceramic capacitor. layout guidelines careful pc board layout is critical to achieve stable operation. the high-voltage section and the switching section of the circuit require particular attention. the high-voltage sections of the layout need to be well sep- arated from the control circuit. most layouts for single- lamp notebook displays are constrained to the long and narrow form factor, so this separation occurs natu- rally. follow these guidelines for good pc board layout: 1) keep the high-current paths short and wide, espe- cially at the ground terminals. this is essential for stable, jitter-free operation, and high efficiency. 2) utilize a star-ground configuration for power and analog grounds. the power and analog grounds should be completely isolated?eeting only at the center of the star. the center should be placed at the exposed backside pad to the qfn package. using separate copper islands for these grounds may simplify this task. quiet analog ground is used for ref, ccv, cci, and ilim (if a resistive voltage- divider is used). 3) route high-speed switching nodes away from sen- sitive analog areas (cci, ccv, ref, v fb , i fb , i sec , ilim). make all pin-strap control input connections (ilim, etc.) to analog ground or v cc rather than power ground or v dd . 4) mount the decoupling capacitor from v cc to gnd as close as possible to the ic with dedicated traces that are not shared with other signal paths. 5) the current-sense paths for lx1 and lx2 to gnd must be made using kelvin-sense connections to guarantee the current-limit accuracy. with 8-pin so mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connecting gnd and lx inside (under- neath) the 8-pin so package. 6) ensure the feedback connections are short and direct. to the extent possible, ifb, vfb, and isec connections should be far away from the high-volt- age traces and the transformer. 7) to the extent possible, high-voltage trace clear- ance on the transformer? secondary should be widely separated. the high-voltage traces should also be separated from adjacent ground planes to prevent lossy capacitive coupling. 8) the traces to the capacitive voltage-divider on the transformer? secondary need to be widely sepa- rated to prevent arcing. moving these traces to opposite sides of the board can be beneficial in some cases (see figure 10). note: dual mosfet n2 is mounted on the bottom side of the pc board directly under n1. high-current primary connection high-voltage secondary connection lamp n1 n2 t1 c4 c2 d1 r2 c3 figure 10. high-voltage components layout example
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface ______________________________________________________________________________________ 23 chip information transistor count: 7116 process: bicmos 28 27 26 25 24 23 22 8910 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 max8709eti max8709aeti thin qfn top view ref ilim lot gnd isec sda scl v cc batt ccv cci ifb n.c. vfb gh2 lx2 bst2 bst1 lx1 gh1 gl1 gl2 pgnd v dd n.c. n.c. n.c. sus pin configuration
max8709/max8709a high-efficiency ccfl backlight controller with smbus interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2005 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qfn thin.eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 d/2 d2/2 l c l c e e l c c l k l l detail b l l1 e xxxxx marking h 1 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- l e/2 common dimensions 3.35 3.15 t2855-1 3.25 3.35 3.15 3.25 max. 3.20 exposed pad variations 3.00 t2055-2 3.10 d2 nom. min. 3.20 3.00 3.10 min. e2 nom. max. ne nd pkg. codes 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220, except exposed pad dimension for t2855-1, t2855-3, and t2855-6. notes: symbol pkg. n l1 e e d b a3 a a1 k 10. warpage shall not exceed 0.10 mm. jedec t1655-1 3.20 3.00 3.10 3.00 3.10 3.20 0.70 0.80 0.75 4.90 4.90 0.25 0.25 0 -- 4 whhb 4 16 0.35 0.30 5.10 5.10 5.00 0.80 bsc. 5.00 0.05 0.20 ref. 0.02 min. max. nom. 16l 5x5 3.10 t3255-2 3.00 3.20 3.00 3.10 3.20 2.70 t2855-2 2.60 2.60 2.80 2.70 2.80 l 0.30 0.50 0.40 -- - -- - whhc 20 5 5 5.00 5.00 0.30 0.55 0.65 bsc. 0.45 0.25 4.90 4.90 0.25 0.65 - - 5.10 5.10 0.35 20l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-1 28 7 7 5.00 5.00 0.25 0.55 0.50 bsc. 0.45 0.25 4.90 4.90 0.20 0.65 - - 5.10 5.10 0.30 28l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. -- - whhd-2 32 8 8 5.00 5.00 0.40 0.50 bsc. 0.30 0.25 4.90 4.90 0.50 - - 5.10 5.10 32l 5x5 0.20 ref. 0.75 0.02 nom. 0 0.70 min. 0.05 0.80 max. 0.20 0.25 0.30 down bonds allowed no yes 3.10 3.00 3.20 3.10 3.00 3.20 t2055-3 3.10 3.00 3.20 3.10 3.00 3.20 t2055-4 t2855-3 3.15 3.25 3.35 3.15 3.25 3.35 t2855-6 3.15 3.25 3.35 3.15 3.25 3.35 t2855-4 2.60 2.70 2.80 2.60 2.70 2.80 t2855-5 2.60 2.70 2.80 2.60 2.70 2.80 t2855-7 2.60 2.70 2.80 2.60 2.70 2.80 3.20 3.00 3.10 t3255-3 3.20 3.00 3.10 3.20 3.00 3.10 t3255-4 3.20 3.00 3.10 no no no no no no no no yes yes yes yes 3.20 3.00 t1655-2 3.10 3.00 3.10 3.20 yes no 3.20 3.10 3.00 3.10 t1655n-1 3.00 3.20 3.35 3.15 t2055-5 3.25 3.15 3.25 3.35 yes 3.35 3.15 t2855n-1 3.25 3.15 3.25 3.35 no 3.35 3.15 t2855-8 3.25 3.15 3.25 3.35 yes 3.20 3.10 t3255n-1 3.00 no 3.20 3.10 3.00 l 0.40 0.40 ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** see common dimensions table 0.15 11. marking is for package orientation reference only. h 2 2 21-0140 package outline, 16, 20, 28, 32, 40l thin qfn, 5x5x0.8mm -drawing not to scale- 12. number of leads shown are for reference only. 3.30 t4055-1 3.20 3.40 3.20 3.30 3.40 ** yes 0.05 00.02 0.60 0.40 0.50 10 ----- 0.30 40 10 0.40 0.50 5.10 4.90 5.00 0.25 0.35 0.45 0.40 bsc. 0.15 4.90 0.25 0.20 5.00 5.10 0.20 ref. 0.70 min. 0.75 0.80 nom. 40l 5x5 max. 13. lead centerlines to be at true position as defined by basic dimension "e", 0.05.

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